Conventionally, NAND flash memories have been developed as nonvolatile semiconductor memory devices. Conventional NAND flash memories adopt what is called the rocket type structure in which the floating electrode protrudes upward. In the rocket type, in order to enhance the controlling power of the control electrode, the control electrode is placed not only on the floating electrode but also between the floating electrodes.
When miniaturization is pursued in the rocket type NAND flash memory, interference occurs between the adjacent memory cell transistors, and malfunctions are made more likely to occur. Furthermore, because of the increase of aspect ratio, processing for inserting the control electrode between the floating electrodes is made difficult. Thus, what is called the flat type structure can be considered. In the configuration of the NAND flash memory of the flat type structure, the interelectrode insulating layer is formed flat, and the control electrode is not inserted between the floating electrodes.
However, in the flat type NAND flash memory, the problem is that the controlling power of the control electrode is weak, and it is difficult to apply an electric field having a sufficient intensity between the active area and the floating electrode. This decreases the amount of charge that can be accumulated in the floating electrode. Thus, the variation of threshold cannot be sufficiently ensured. Furthermore, if the floating electrode is thinned to enhance the applied electric field, activation of polycrystalline silicon constituting the floating electrode is made difficult. Thus, the floating electrode is made less likely to trap electrons. In this context, there is proposed a technique in which a charge trap layer for trapping electrons is provided on the floating electrode independently of the floating electrode.